In the field of digital technology, it is quite common to have systems operating on a synchronous basis with intercommunication with a multiplicity of digital modules. As operations proceed, each of the digital modules will contain various pieces of information being handled or processed and also containing data on the various control states of each of the modules.
These systems modules may consist of multiple numbers of processors, memory units and input/output units as is commonly provided in computer system networks.
In a synchronous system, all system modules will operate on the same system clock source, that is to say, all the system clocks are at the same frequency and operated synchronously.
As the multiple modules communicate with each other and process and manage their own individual data, each of the modules contains various valuable pieces of information data. For example, there are registers containing data words and program instruction words. Further, each module will operate in various control states as evidenced by numerous control flip-flops (which may number in the thousands) and which will be on/off in millions of possible combinations. The appropriate and proper combination of the control flip-flops is called the "control state of the module". All state and data information is actually vital to the proper execution of the overall system operation. Not only is this data necessary for proper computer operations, but also it is necessary for testing the hardware and for hardware and software problem-fixing and general system maintenance.
As often occurs, the entire system network and the various modules must be shutdown or turned off in order to stop the handling or processing of information data in each module. When a stop condition is signalled, it is mandatory that all modules should stop simultaneously on the same clock pulse. Any failure to stop each module at the same moment in time would lead to data corruption, lost data and inaccurate data. The failure to stop each of the modules altogether at the same moment would be analogous to having a four cylinder engine which was shutdown, but one piston of the four cylinder engine would have kept on moving while the other pistons would have stopped. In this case, the engine would not be any longer usable in a recoverable condition after such a disorderly stop.
Likewise, in a multiple digital module system, any inconsistency in the time moments of stopping in the various modules could lead to very severe consequences, as mentioned, of lost data and of data corruption and loss of information as to various state conditions of the individual modules.
The present invention is devoted to providing means in multiple digital module systems whereby the stopping or halting operation can be done neatly, quickly, efficiently and, at the same moment of time in order to preserve all the data information integrity and state condition information in each of the modules so that an orderly stop will have occurred and so that subsequently a start up can be done in an orderly fashion.